Lec 02-20-2025: Sequential Circuits, Latches & Flip-Flops

A combinational circuit has no memory, its output depends only on its current inputs. That’s fine for things like adders, but it means the circuit can’t remember anything between moments. Sequential circuits fix this by adding memory: the output depends not just on current inputs, but on past inputs too. This is what allows a circuit to have state — a stored value that persists and influences future behavior.

The memory in a sequential circuit is held in flip-flops, which store one bit each. A clock is a signal that oscillates between 0 and 1 at a regular rate — it acts as a heartbeat for the circuit, controlling when stored values are allowed to change and keeping everything synchronized.

Note

For this class we’ll only worry about synchronous sequential circuits — ones where state only changes at specific, clock-controlled moments.

Sequential Circuits

A synchronous sequential circuit is built around a feedback loop:

• External inputs feed into a combinational circuit
• The combinational circuit computes the outputs and the next state
• The next state gets stored in flip-flops on the next clock change
• The flip-flop outputs (the current state) feed back into the combinational circuit as additional inputs

The clock timing diagram (part b) shows the regular square wave that drives this — state only updates at specific points in the clock cycle, so the circuit steps forward in discrete, predictable ticks rather than continuously reacting to every input change.

RS Latch

The most basic memory element is the RS latch, built from two cross-coupled NAND gates. It has two inputs — Set ($S$) and Reset ($R$) — and two complementary outputs $Q$ and $Q'$.

Once we understand what the latch does, we can abstract away the internal gates and represent it as a single block — inputs on the left, outputs on the right:

This box notation is the standard way to represent flip-flops and latches in circuit diagrams. $Q$ and $Q'$ are intended to be complementary outputs — when one is $1$, the other is $0$.

The cross-coupling is what gives the latch memory: each gate’s output feeds back into the other gate’s input, so the circuit holds its last state even after the inputs return to 0.

The main behavior of the RS latch is as follows:

• Set ($S=1$, $R=0$): forces $Q=1$, $Q'=0$
• Reset ($S=0$, $R=1$): forces $Q=0$, $Q'=1$
• Hold ($S=0$, $R=0$): $Q$ and $Q'$ retain their previous values
• Forbidden ($S=1$, $R=1$): both outputs driven to $1$, which breaks the $Q$/$Q'$ complementary relationship — this state must be avoided

The characteristic table summarizes all possible input combinations and the resulting next state:

$$\begin{array}{cc|c} S & R & Q(t+1) \\ \hline 0 & 0 & Q(t) \\ 0 & 1 & 0 \\ 1 & 0 & 1 \\ 1 & 1 & ? \\ \end{array}$$

RS Flip-Flop

A plain RS latch responds to inputs immediately, so any glitch on $S$ or $R$ can change the output. A clock input (enable) fixes this by acting as a gatekeeper — the latch only responds when clock = 1 (when the clock is high).

When clock = 0, both AND gates block the inputs and the flip-flop holds its state regardless of $S$ and $R$. When clock = 1, the inputs pass through:

$$\begin{array}{c|cc|c} \text{Clk} & S & R & Q(t+1) \\ \hline 0 & X & X & Q(t) \\ 1 & 0 & 0 & Q(t) \\ 1 & 0 & 1 & 0 \\ 1 & 1 & 0 & 1 \\ 1 & 1 & 1 & ? \\ \end{array}$$

The clock gates the inputs but doesn’t remove the forbidden state.

$S=1$, $R=1$ with clock=1 is still undefined. That limitation is what motivates the D flip-flop next.

D Flip-Flop

The RS flip-flop still has the forbidden state problem. The D flip-flop eliminates it by having just one input D, where $S = D$ and $R = D'$ are wired internally — since $D$ and $D'$ are always opposites, the forbidden state can never occur.

The D flip-flop has the simplest characteristic table of any flip-flop — the output just follows the input:

$$\begin{array}{c|c} D & Q(t+1) \\ \hline 0 & 0 \\ 1 & 1 \\ \end{array}$$

Other Flip-Flop Types

Beyond RS and D, two other flip-flop types come up often in sequential circuit design.

JK Flip-Flop

The JK flip-flop is an extension of the RS flip-flop that eliminates the forbidden state. $J$ acts like Set and $K$ acts like Reset, but when both $J=1$ and $K=1$ (which was forbidden in RS), the flip-flop simply toggles — $Q$ flips to whatever it wasn’t. This makes the JK flip-flop the most versatile of the common types.

The $J=1$, $K=1$ case is what sets JK apart — instead of a forbidden state, it toggles $Q$:

$$\begin{array}{cc|c} J & K & Q(t+1) \\ \hline 0 & 0 & Q(t) \\ 0 & 1 & 0 \\ 1 & 0 & 1 \\ 1 & 1 & Q'(t) \\ \end{array}$$

T Flip-Flop

The T (Toggle) flip-flop has a single input $T$. When $T=0$ the output holds; when $T=1$ the output toggles. It’s essentially a JK flip-flop with $J$ and $K$ tied together, and is particularly useful for building counters.

The toggle behavior is the simplest possible: $T=0$ holds, $T=1$ flips:

$$\begin{array}{c|c} T & Q(t+1) \\ \hline 0 & Q(t) \\ 1 & Q'(t) \\ \end{array}$$