Lec 02-25-2025: Sequential Circuits & Master-Slave Flip Flop

Master-Slave Flip Flop

In the previous lecture, we introduced clocked flip-flops, which are designed to only change state on a clock edge, but there’s still a problem when multiple flip-flops need to change state together. Consider a circuit with two flip-flops, A and B, that are supposed to swap states on the same clock edge:

Each f/f must change state instantly at the same time, otherwise we might end up at the wrong state. For example, if A updates before B, then B might read A’s new value instead of A’s old value when computing its own next state, producing a wrong result.

The master-slave approach solves this by splitting each flip-flop into two stages. The first stage (master) captures the input during one clock phase, and the second stage (slave) transfers that captured value to the output during the opposite phase. This way, the output only changes after the input has already been locked in — the two stages can never interfere with each other.

The master uses the clock directly, and the slave uses an inverted copy of the clock — so when the master is open (clock=1), the slave is locked, and vice versa. The output Q of the master (called Y) becomes the input to the slave.

The clock behaves as such:

Signal	clock = 1	clock = 0
Y	Follows D	Holds last value
Q	Holds last value	Follows Y

So the final output Q only ever changes on the falling edge of the clock (the transition from 1 to 0), which is when the slave unlocks and copies whatever Y was holding.

When D and C are 1, Y follows D and the state of the master becomes 1. Once C drops to 0 (negative edge), the master locks in whatever Y was holding, and that is when the slave unlocks and copies Y into Q.

Given C and D, we can determine Y and Q by considering the following:

• Y: output of the master f/f
• Q: output of the slave f/f

Behavior of Y:

• When clock is 1, Y is a copy of D
• When clock is 0, Y doesn’t change

Behavior of Q:

• When clock is 0, Q is a copy of Y
• When clock is 1, Q doesn’t change

Designing a Clocked Sequential Circuit with JK Flip Flops

Now that we know how flip-flops work, we can use them to design a circuit that implements a specific behavior from a state specification. The JK flip-flop is a common choice for this kind of design because of its flexibility in controlling state transitions, as is apparent from its characteristic table.

The process follows a standard recipe: write down the state transitions, figure out what J and K inputs are needed to produce each transition, then use K-maps to minimize the resulting Boolean expressions into circuit logic.

Say we want to design a clocked sequential circuit for the following specification using JK flip flops:

$$0 \to 1 \text{ by a 1}$$ $$1 \to 2 \text{ by a 0}$$ $$2 \to 3 \text{ by a 1}$$ $$3 \to 0 \text{ by a 1}$$

Which corresponds to the below state diagram. Since a state diagram needs a transition for every possible input in every state, we can extrapolate the missing transitions as being “otherwise, stay in the same state” (i.e. self-loops on each state for where a transitiion wasn’t specified):

We use two flip-flops A and B to represent the four states (00, 01, 10, 11), with an input X determining which transition to take.

The first step is to enumerate every combination of present state and input, and look up the corresponding next state from the diagram:

$$\begin{array}{cc|c|cc|cccc} \text{Present State} & & \text{Input} & \text{\ \ \ \ Next State} & & & \text{f/f inputs} & & \\ \hline A & B & X & A & B & J_A & K_A & J_B & K_B \\ \hline 0 & 0 & 0 & 0 & 0 & & & & \\ 0 & 0 & 1 & 0 & 1 & & & & \\ 0 & 1 & 0 & 1 & 0 & & & & \\ 0 & 1 & 1 & 0 & 1 & & & & \\ 1 & 0 & 0 & 1 & 0 & & & & \\ 1 & 0 & 1 & 1 & 1 & & & & \\ 1 & 1 & 0 & 1 & 1 & & & & \\ 1 & 1 & 1 & 0 & 0 & & & & \\ \end{array}$$

The next step is to fill in the $J$ and $K$ columns. This is where the excitation table comes in. A regular characteristic table tells you what $Q(t+1)$ will be given $J$ and $K$, but here we’re working in reverse: we already know $Q(t)$ and $Q(t+1)$ (from the state diagram), and we need to figure out what $J$ and $K$ inputs would cause that transition. The excitation table gives us exactly that mapping:

$$\begin{array}{cc|cc} Q(t) & Q(t+1) & J & K \\ \hline 0 & 0 & 0 & X \\ 0 & 1 & 1 & X \\ 1 & 0 & X & 1 \\ 1 & 1 & X & 0 \\ \end{array}$$

The $X$ entries are don’t-cares — when a flip-flop is being set ($J$), $K$ doesn’t matter, and vice versa. This is actually one of the reasons JK flip-flops are useful for this kind of design: the don’t-cares give the K-map minimization more flexibility later.

For each row in the state transition table, we apply the excitation table independently to flip-flop A and flip-flop B. Turning our focus on the first row for flip flop A, we’ll look at present state $A$, next state $A$, and $J_A$, $K_A$. Since current state of a $A$ is 0, and the next state of $A$ is at 0, then we look at the excitation table for where $Q(t)=0$ and $Q(t+1)=0$, which tells us that in order to drive this transition, then $J_A$ must be 0 and $K_A$ can be anything (X). We repeat this process for every row and for both flip-flops, filling in the $J$ and $K$ columns:

$$\begin{array}{cc|c|cc|cccc} \text{Present State} & & \text{Input} & \text{\ \ \ \ Next State} & & & \text{f/f inputs} & & \\ \hline A & B & X & A & B & J_A & K_A & J_B & K_B \\ \hline 0 & 0 & 0 & 0 & 0 & 0 & X & 0 & X \\ 0 & 0 & 1 & 0 & 1 & 0 & X & 1 & X \\ 0 & 1 & 0 & 1 & 0 & 1 & X & X & 1 \\ 0 & 1 & 1 & 0 & 1 & 0 & X & X & 0 \\ 1 & 0 & 0 & 1 & 0 & X & 0 & 0 & X \\ 1 & 0 & 1 & 1 & 1 & X & 0 & 1 & X \\ 1 & 1 & 0 & 1 & 1 & X & 0 & X & 0 \\ 1 & 1 & 1 & 0 & 0 & X & 1 & X & 1 \\ \end{array}$$

K-Maps

With the table filled in, we can minimize each of the four input expressions using K-maps. Each K-map has three variables: A, B, and X.

$J_A$:

$$J_A = BX'$$

$K_A$:

$$K_A = BX$$

$J_B$:

$$J_B = X$$

$K_B$:

$$K_B = A'X' + AX = \overline{A \oplus X}$$

Derived Equations

$$J_A = BX' \qquad K_A = BX \qquad J_B = X \qquad K_B = \overline{A \oplus X}$$

Circuit Diagram